In a multi-core or multi-thread microprocessor, it is often necessary to have communication between two or more cores or threads. For example, core to core communications may be required in the boot-up firmware (e.g., the basic input/output system, or BIOS) when certain elements of the processor are shared between the cores, such as a Level 3 (L3) cache. In such cases, it becomes necessary to control both cores during initialization or in the event of an interrupt or exception to prevent consumption of an error. Communication during initialization is frequently necessary to allow one core or thread to test and initialize shared structures while another core or thread waits for completion. It is also possible to have two or more cores or threads performing tests of different portions of the structures and to communicate the results between them.
In the case of an interrupt or exception, an interrupt/exception handler normally must communicate between the cores in order to perform recovery. In addition, firmware routines often must run concurrently on each core of a dual core processor or, potentially, on each thread of a dual thread processor, necessitating communication between the two processor cores in order to synchronize progress. Operating System (OS) resources are normally not available to the boot-up firmware, nor is access to memory during portions of firmware execution. Therefore, an alternative mechanism is needed for core to core or thread to thread communication.
One previous approach is to use shared registers to communicate between cores. However, great care must be taken with this approach to coordinate when each core is reading or writing the shared registers, to avoid conflicts and invalid data. A hardware semaphore may be used to provide this coordination. However, the use of a hardware semaphore tends to complicate the firmware and increases the likelihood of software errors (“bugs”). In particular, it prevents the use of identical code paths by each core or thread when executing firmware, by requiring various branches and/or jumps to account for proper addressing of registers. Similar problems exist with respect to thread to thread communications in a multi-thread processor. Hence, what is needed is a better technique for core to core or thread to thread communications in a multi-core or multi-thread microprocessor.